View AD74111YRUZ-REEL_7393254.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. ad74111 low cost, low power mono audio codec features 2.5 v mono audio codec with 3.3 v tolerant digital interface supports 8 khz to 48 khz sample rates supports 16-/20-/24-bit word lengths multibit - modulators with ?erfect differential linearity restoration?for reduced idle tones and noise floor data directed scrambling dac ?least sensitive to jitter performance (20 hz to 20 khz) 85 db adc dynamic range 93 db dac dynamic range programmable adc gain on-chip volume control for dac channel software controllable clickless mute supports 256 f s , 512 f s , and 768 f s master mode clocks master clock prescaler for use with dsp master clocks on-chip reference 16-lead tssop package applications digital video camcorders (dvc) portable audio devices (walkman , pdas, and so on) audio processing voice processing telematic systems general-purpose analog i/o functional block diagram gain stage digital filter adc vin capp capn dvdd2 avdd dvdd1 dac channel volume control digital filter vout agnd refcap din dout dfs dclk dgnd mclk reset - dac modulator - modulator serial data port reference general description the ad74111 is a front-end processor for general-purpose audio and voice applications. it features a multibit - a/d conversion channel and a multibit - d/a conversion channel. the adc channel provides >67 db thd+n and the dac channel pro- vides >88 db thd+n, both over an audio signal bandwidth. the ad74111 is particularly suitable for a variety of applications where mono input and output channels are required, including audio sections of digital video camcorders, portable personal audio devices, and telematic applications. its high quality perform ance also makes it suitable for speech and telephony applications such as speech recognition and synthesis, and modern feature phones. an on-chip reference voltage is included but can be powered down and bypassed by an external reference source if required. the ad74111 offers sampling rates that, depending on mclk selection and mclk divider ratio, range from 8 khz in the voiceband range to 48 khz in the audio range. the ad74111 is available in a 16-lead tssop package option and is specified for the automotive temperature range of ?0 c to +105 c.
rev. 0 ? ad74111?pecifications (avdd = 2.5 v 5%, dvdd2 = 2.5 v 5%, dvdd1 = 2.5 v 5%, f mclk = 12.288 mhz, f s = 48 khz, t a = t min to t max , unless otherwise noted.) parameter conditions min typ max unit analog-to-digital converters adc resolution 24 bits signal to noise ratio (snr) f s = 16 khz 70 77 db dynamic range (20 hz to 20 khz, ?0 db input) no filter f s = 48 khz 85 db f s = 16 khz 78 85 db with a-weighted filter f s = 48 khz 87 db total harmonic distortion + noise f s = 48 khz, pga = 0 db ?7 db f s = 16 khz ?5 db programmable input gain 12 db gain step size 3db offset error ?5 +30 +80 mv full-scale input voltage 0.5 v rms input resistance 4k ? input capacitance 15 pf common-mode input volts 1.125 v crosstalk adc input signal = 1.0 khz, 100 db 0 db; dac output = dc digital-to-analog converters dac resolution 24 bits signal to noise ratio (snr) f s = 16 khz 80 89 db dynamic range (20 hz to 20 khz, ?0 db input) no filter f s = 48 khz 93 db f s = 16 khz 84 93 db with a-weighted filter f s = 48 khz 95 db total harmonic distortion + noise f s = 48 khz ?8 db f s = 16 khz ?8 ?1 db db dc accuracy offset error ?5 ?0 +50 mv gain error ?.9 +0.175 +0.8 db volume control step size (1024 linear steps) 0.098 % volume control range (max attenuation) ?0 db mute attenuation ?00 db de-emphasis gain error 0.1 db full-scale output voltage 0.5 v rms output resistance 145 ? common mode output volts 1.125 v crosstalk signal input adc = agnd; 95 db dac output level = 1.0 khz, 0 db reference (internal) absolute voltage, v ref 1.125 v v ref tc 50 ppm/ c
rev. 0 ad74111 ? table i. current summary (avdd = 2.5 v, dvdd1 = 2.5 v, dvdd2 = 2.5 v) 1, 2, 3 avdd dvdd1 dvdd2 total current conditions current (ma) current (ma) current (ma) (max)(ma) adc, reference, ref-amp on 6.11 (6.11) 0.15 (0.43) 0.72 (2.10) dac, reference, ref-amp on 3.80 (4.0) 0.15 (0.43) 0.85 (2.23) reference, ref-amp on 0.60 (0.60) 0.15 (0.43) 0.27 (0.50) all sections on 8.60 0.15 (0.43) 1.72 (4.80) 15.35 power-down mode 0.035 0.15 (0.43) 0.49 (0.49) 2.6 notes 1 all values are typical, unless otherwise noted. 2 max values are quoted with dvdd1 = 3.6 v. 3 sample rates quoted are for 16 khz and (48 khz). parameter conditions min typ max unit adc decimation filter * f s = 48 khz pass band 21.5 khz pass-band ripple 0.2 mdb transition band 5 khz stop band 26.5 khz stop-band attenuation 120 db group delay 910 s low group delay mode 87 s dac interpolation filter * f s = 48 khz pass band 21.5 khz pass-band ripple 10 mdb transition band 5 khz stop band 26.5 khz stop-band attenuation 75 db group delay 505 s low group delay mode 55 s logic input v inh , input high voltage dvdd1 ?0.8 dvdd1 v v inl , input low voltage 0 0.8 v input current ?0 +10 a input capacitance 10 pf logic output v oh , output high voltage dvdd1 ?0.4 dvdd1 v v ol , output low voltage 0 0.4 v three-state leakage current ?0 +10 a power supplies avdd 2.375 2.625 v dvdd2 2.375 2.625 v dvdd1 2.375 3.6 v power supply rejection ratio 1 khz, 300 mv p-p signal at analog supply pins 72 db 50/60 hz, 300 mv p-p signal at analog supply pins 73 db * guaranteed by design. specifications subject to change without notice.
rev. 0 ? ad74111 timing characteristics (avdd = 2.5 v 5%, dvdd2 = 2.5 v 5%, dvdd1 = 3.3 v 10 %, f mclk = 12.288 mhz, f s = 48 khz, t a = t min to t max , unless otherwise noted.) parameter min max unit comments master clock and reset t mh mclk high 25 ns t ml mclk low 25 ns t res reset low 10 ns t rs din setup time 5 mclks to reset rising edge 1 t rh din setup time 5 mclks to reset rising edge 1 serial port t ch dclk high 2 20 ns t cl dclk low 2 20 ns t fd dfs delay 5 ns from dclk rising edge 3 t fs dfs setup time 5 ns to dclk falling edge t fh dfs hold time 15 ns from dclk falling edge t dd dout delay 30 ns from dclk rising edge t ds din setup time 5 ns to dclk falling edge t dh din hold time 15 ns from dclk falling edge t dt dout three-state 40 ns from dclk rising edge 4 notes 1 determines master/slave mode operation. 2 applies in slave mode only. 3 applies in master mode only. 4 applies in multiframe-sync mode only. mclk t mh reset t ml t res t rs t rh din figure 1. mclk and reset timing msb msb?1 t fs dfs dclk din dout msb msb?2 msb?1 msb?2 t fh t fd t dd t ch t cl t ds t dh figure 2. serial port timing 100 a i ol 100 a i oh c l 50pf to output pin dvdd1 2 figure 3. load circuit for digital output timing specifications
rev. 0 ad74111 ? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad74111 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * (t a = 25 c, unless otherwise noted.) avdd, dvdd2 to agnd, dgnd . . . . . . . ?.3 v to +3.0 v dvdd1 to agnd, dgnd . . . . . . . . . . . . . ?.3 v to +4.5 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v digital i/o voltage to dgnd . . . . . . ?.3 v to dvdd1 + 0.3 v operating temperature range automotive (y version) . . . . . . . . . . . . . . ?0 c to +105 c storage temperature range . . . . . . . . . . . . . ?5 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150 c 16-lead tssop, ja thermal impedance . . . . . . . . 150.4 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. temperature range parameter min max unit specifications guaranteed ?0 +105 ? storage ?5 +150 ? ordering guide model range package ad74111yru ?0? to +105? ru-16
rev. 0 ? ad74111 pin configuration vin capp refcap agnd dgnd dvdd2 dvdd1 mclk vout capn avdd r eset dout dfs din dclk 1 2 3 16 4 15 5 14 6 13 7 12 8 11 10 9 ad74111 top view (not to scale) pin function descriptions pin no. mnemonic i/o description 1 dclk i/o serial clock 2d in i serial data input. the state of din on the rising edge of reset determines the operating mode of the interface. see the selecting master or slave mode section for more information. 3 dfs i/o frame synchronization signal 4 dout o serial data output 5 reset ip ower-down/reset input 6 avdd analog 2.5 v power supply connection 7 capn adc filter capacitor (negative) 8 vout o dac analog output 9v in i adc analog input 10 capp adc filter capacitor (positive) 11 refcap i/o internal reference decoupling capacitor. can also be used for connection of an external reference. 12 agnd analog ground connection 13 dgnd digital ground connection 14 dvdd2 digital 2.5 v power supply connection (core) 15 dvdd1 digital power supply connection (interface) 16 mclk i external master clock input
rev. 0 t ypical performance characteristics?d74111 ? frequency ? normalized to f s ?150 01.0 0.25 magnitude ? db 0.5 0.75 0 ?100 ?50 tpc 1. adc composite filter response frequency ? normalized to f s ?150 0 1.0 0.25 magnitude ? db 0.5 0.75 0 ?100 ?50 tpc 2. adc composite filter response low group delay enabled 1.0 0.5 0 ?0.5 ?1.0 0 0.1 0.2 0.3 0.4 0.5 frequency ? normalized to f s magnitude ? mdb tpc 3. adc composite filter response (pass-band section) frequency ? normalized to f s ?120 0 1.0 0.25 magnitude ? db 0.5 0.75 0 ?80 ?40 tpc 4. dac composite filter response frequency ? normalized to f s ?120 ?80 ?40 01.0 0.25 magnitude ? db 0.5 0.75 0 tpc 5. dac composite filter response low group delay enabled 0 0.1 0.2 0.3 0.4 0.5 frequency ? normalized to f s 10 5 ?5 ?10 magnitude ? mdb 0 tpc 6. dac composite filter response (pass-band section)
rev. 0 ? ad74111 functional description general description the ad74111 is a 2.5 v mono codec. it comprises an adc and dac channel with single-ended input and output. the adc has a programmable gain stage and the dac has programmable volume control. each of these sections is described in further detail below. the ad74111 is controlled by means of a flexible serial port (sport) that can be programmed to accommodate many industry standard dsps and microcontrollers. the ad74111 can be set to operate as a master or slave device. the ad74111 can be set to operate with sample rates of 8 khz to 48 khz, depending on the values of mclk and the mclk prescalers. on-chip digital filtering is provided as part of the dac and adc channels with a low group delay option to reduce the delays through the filters when operating at lower sample rates. figure 4 shows a block diagram of the dac and adc channel in the ad74111. figures 5a and 5b show block diagrams of the filter arrangements of the adc and dac filters. adc section the ad74111 contains a multibit sigma-delta adc. the adc has a single input pin with additional pins for decoupling/filter capacitors. the adc channel has an independent input amplifier gain stage that can be programmed in steps of 3 db, from 0 db to 12 db. the input amplifier gain settings are set by program- ming the appropriate bits in control register e. the adc can also be muted under software control. the ad74111 input channel employs a multibit sigma-delta conversion technique that provides a high resolution output with system filtering imple- mented on-chip. sigma-delta converters employ a technique known as oversampling, where the sampling rate is many times the highest frequency of interest. in the case of the ad74111, the oversampling ratio is 64 and a decimation filter is used to reduce the output to standard sample rates. the maximum sample rate is 48 khz. dac data 16-/20-/24- bits 5 bits /4 prescalers (/1 to /12) - adc modulator sinc filter (/8) decimator (/8) mclk adc data 16-/20-/24- bits adc input adc modulator clock dac o/p dac modulator clock /2 - dac modulator interpolator ( 16) interpolator ( 8) figure 4. adc and dac engine sample rate ? khz 54 84 48 16 thd+n ? db 24 40 58 62 66 70 74 78 32 tpc 7. adc thd+n vs. sample rate sample rate ? khz 78 848 16 thd+n ? db 24 40 80 82 84 86 88 90 32 tpc 8. dac thd+n vs. sample rate
rev. 0 ad74111 ? adc modulator 64 f s 5th order comb filter half-band 8 f s 4 f s comb compensation 2 f s half-band f s adc result low group delay output figure 5a. adc filter section dac modulator 128 f s 16 zero order hold half-band filter 8 f s 4 f s zero order hold sinc compensation filter 2 f s half-band? filter f s dac input low group delay input figure 5b. dac filter section adc, capp, and capn pins the adc channel requires two external capacitors to act as charge reservoirs for the switched capacitor inputs of the sigma- delta modulator. these capacitors isolate the outputs of the pga stage from glitches generated by the sigma-delta modulator. the capacitor also forms a low-pass filter with the output impedance of the pga (approximately 124 ?), which helps to isolate noise from the modulator engine. the capacitors should be of good quality, such as npo or polypropylene film, with values from 100 pf to 1 nf and should be connected to agnd. peak readback the ad74111 can store the highest adc value to facilitate level adjustment of the input signal. programming the peak enable bit in control register e with a 1 will enable adc peak level reading. the peak value is stored as a 6-bit number from 0 db to ?3 db in 1 db steps. reading control register f will give the highest adc value since the bit was set. the adc peak register is automatically cleared after reading. decimator section the digital decimation filter has a pass-band ripple of 0.2 mdb and a stop-band attenuation of 120 db. the filter is an fir type with a linear phase response. the group delay at 48 khz is 910 s. output sample rates up to 48 khz are supported. input signal swing the adc input has an input range of 0.5 v rms/1.414 v p-p about a bias point equal to v refcap . figure 6 shows a typical input filter circuit for use with the ad74111. vin v agnd 1.414v p-p 51 10nf npo 47 f figure 6. typical input circuit dac section the ad74111 dac channel has a single-ended, analog output. the dac has independent software controllable mute and volume control functions. control register g controls the attenuation factor for the dac. this register is 10 bits wide, giving 1024 steps of attenuation. the ad74111 output channel employs a multibit sigma-delta conversion technique that provides a high quality output with system filtering implemented on-chip. output signal swing the dac has an output range of 0.5 v rms/1.414 v p-p about a bias point equal to v refcap (see figure 7). v refcap 1.414v p-p 820 2n2f npo vout figure 7. typical output circuit low group delay it is possible to bypass much of the digital filtering by enabling the low group delay function in control register c. by reduc- ing the amount of filtering the ad74111 applies to input and output samples, the time delay between the sampling interval and when the sample is available is greatly reduced. this can be of benefit in applications such as telematics, where minimal time delays are important. when the low group delay function is enabled, the sample rate becomes imclk/128. reference the ad74111 features an on-chip reference whose nominal value is 1.125 v. a 100 nf ceramic and 10 f tantalum capacitor applied at the refcap pin are necessary to stabilize the reference. (see figure 8.) refcap 0.1 f 10 f figure 8. reference decoupling if required, an external reference can be used as the reference source of the adc and dac sections. this may be desirable in situations where multiple devices are required to use the same value of reference or because of a better temperature coefficient specification. the internal reference can be disabled via control register a and the external reference applied at the refcap pin (see figure 9). external references should be of a suitable value such that the voltage swing of the inputs or outputs is not affected by being too close to the power supply rails and should be adequately decoupled.
rev. 0 ?0 ad74111 refcap 1.125v external reference figure 9. external reference master clocking scheme the update rate of the ad74111? adc and dac channels requires an internal master clock (imclk) that is 256 times the sample update rate (imclk = 256 f s ). to provide some flex- ibility in selecting sample rates, the device has a series of three master clock prescalers that are programmable and allow the user to choose a range of convenient sample rates from a single external master clock. the master clock signal to the ad74111 is applied at the mclk pin. the mclk signal is passed through a series of three programmable mclk prescaler (divider) circuits that can be selected to reduce the resulting internal mclk (imclk) frequency if required. the first and second mclk prescalers provide divider ratios of 1 (pass through), 2, 3; while the third prescaler provides divider ratios of 1 (pass through), 2, 4. imclk p rogrammable mclk divider c ontrol register /1 /2 /3 /1 /2 /4 pre scaler 2 pre scaler 3 mclk /1 /2 /3 pre scaler 1 figure 10. mclk divider the divider ratios allow a more convenient sample rate selection from a common mclk, which may be required in many voice related applications. control register b should be programmed to achieve the desired divider ratios. selecting sample rates the sample rate at which the converter runs is always 256 times the imclk rate. imclk is the internal master clock and is the output from the master clock prescaler. the default sample rate is 48 khz (based on an external mclk of 12.288 mh z). in this mode, the adc modulator is clocked at 3.072 mhz and the dac modulator is clocked at 6.144 mhz. sample rates that are lower than mclk/256 can be achieved by using the mclk prescaler. example 1: f samp = 48 khz and 8 khz required mclk = 48 khz 256 = 12.288 mhz to provide 48 khz f samp . for f samp = 8 khz, it is necessary to use the 3 setting in prescaler 1, the 2 setting in prescaler 2, and pass through in prescaler 3. this results in an imclk = 8 khz 256 = 2.048 mhz (= 12.288 mhz/6). example 2: f samp = 44.1 khz and 11.025 khz required mclk = 44.1 khz 256 = 11.2896 mhz to provide 44.1 khz f samp . for f samp = 11.025 khz, it is necessary to use the 1 setting in prescaler 1 and the 4 setting in prescaler 2, and pass through in prescaler 3. this results in an imclk = 11.025 khz 256 = 2.8224 mhz (= 11.2896 mhz/4). resetting the ad74111 the ad74111 can be reset by bringing the reset pin low. following a reset, the internal circuitry of the ad74111 ensures that the internal registers are reset to their default settings and the on-chip ram is purged of previous data samples. the din pin is sampled to determine if the ad74111 is required to oper ate in master or slave mode. the reset process takes 3072 mclk periods, and the user should not attempt to program the ad74111 during this time. power supplies and grounds the ad74111 features three separate supplies: avdd, dvdd1, and dvdd2. avdd is the supply to the analog section of the device and must be of sufficient quality to preserve the ad74111? performance characteristics. it is nominally a 2.5 v supply. dvdd1 is the supply for the digital interface section of the device. it is fed from the digital supply voltage of the dsp or controller to which the device is interfaced and allows the ad74111 to interface with devices operating at supplies of between 2.5 v ?5% to 3.3 v + 10%. dvdd2 is the supply for the digital core of the ad74111. it is nominally a 2.5 v supply. accessing the internal registers the ad74111 has seven registers that can be programmed to control the functions of the ad74111. each register is 10 bits wide and is written to or read from using a 16-bit write or read operation, with the exception of control register f, which is read-only. table v shows the format of the data transfer operation. the control word is made up of a read/write bit, the register address, and the data to be written to the device. note that in a read operation the data field is ignored by the device. access to the control registers is via the serial port through one of the operating modes described below. serial port the ad74111 contains a flexible serial interface port that is used to program and read the control registers and to send and receive dac and adc audio data. the serial port is compatible with many popular dsps and can be programmed to operate in a variety of modes, depending on which one best suits the dsp being used. the serial port can be set to operate as a master or slave device, as discussed below. figure 11 shows a timing diagram of the serial port.
rev. 0 ad74111 ?1 msb msb?1 t fs dfs dclk din dout msb msb?2 msb?1 msb?2 t fh t fd t dd t ch t cl t ds t dh figure 11. serial port (sport) timing serial port operating modes the serial port of the ad74111 can be programmed to operate in a variety of modes depending on the requirements and flex- ibility of the dsp to which it is connected. the two principal modes of operation are mixed mode and data mode. mixed mode mixed mode allows the control registers of the ad74111 to be programmed and read back. it also allows data to be sent to the dacs and data to be read from the adcs. in mixed mode, there are separate data slots, each with its own frame synchroni- zation signal (dfs) for control and dac or adc information. the ad74111 powers up in mixed mode by default to allow the control registers to be programmed. figure 13 shows the default setting for mixed mode. data mode data mode can be used when programming or reading the control registers is no longer required. data mode provides a frame synchronization (dfs) pulse for each sample of data. once the part has been programmed into data mode, the only way to change the control registers is to perform a hardware reset to put the ad74111 back into mixed mode. figure 15 shows the default setting for data mode. data-word length the ad74111 can be programmed to send dac audio data and receive adc audio data in different word length formats of 16, 20, or 24 bits. the default mode is 16 bits, but this can be changed by programming control register c for the appropriate word length. selecting master or slave mode the initial operating mode of the ad74111 is determined by the state of the din pin following a reset. if the din pin is high during this time, slave mode is selected. in slave mode, the dfs and dclk pins are inputs and the control signals for these pins must be provided by the dsp or other controller. if the din pin is low immediately following a reset, the ad74111 will operate in master mode. master mode operation in master mode, the dfs and dclk pins are outputs from the ad74111. this is the easiest mode in which to use the ad74111 because the correct timing relationship between sample rate, dclk, and dfs is controlled by the ad74111. slave mode operation in slave mode, the dfs and dclk pins are inputs to the ad74111. care needs to be exercised when designing a system to operate the ad74111 in this mode as the relationship between the sample rate, dclk, and dfs needs to be controlled by the dsp or other controller and must be compatible with the inter- nal dac/adc engine of the ad74111. figure 12 shows a block diagram of the dac engine and the ad74111? serial port. the sample rate for the dac engine is determined by the mclk and mclk prescalers. the dac engine will read data from the dac data register at this rate. it is therefore important that the serial port is updated at the same rate, as any error between the two will accumulate and eventually cause the dac engine to have to resynchronize with the serial port, which will cause erroneous values on the dac output pins. dac engine dac data register load dat vout resync * * resync is only used when the dac becomes unsynchronized with the serial port serial port dfs din figure 12. dac engine in most cases, it is easy to keep a dsp in synchronization with the ad74111 if they are both run from the same clock or the dsp clock is a multiple of the ad74111? mclk. in this case,
rev. 0 ?2 ad74111 table ii. serial mode selection crd:2 crc:5, 4 crd:3 dsp word operating dm /mm mode width mode figure 00 16 16-bit data mode 15 01 16 32-bit data mode 19 10 16 16-bit mixed mode 13 11 16 32-bit mixed mode 17 00 >16 16-bit data mode 16 01 >16 32-bit data mode 20 10 >16 16-bit mixed mode 14 11 >16 32-bit mixed mode 18 dfs (mm16) din 1/ f s status (16 bits) dout status (16 bits) 128 dclks (normal mode) 256 dclks (fast mode) control (16 bits) dac (16 bits) status (16 bits) adc (16 bits) control (16 bits) dac (16 bits) status (16 bits) adc (16 bits) figure 13. 16-bit mixed mode, word length = 16 bits 16 dclks dfs (mm16) din 1/ f s dout 128 dclks (normal mode) 256 dclks (fast mode) control (16 bits) status (16 bits) dac data (24 bits) adc data (24 bits) control (16 bits) status (16 bits) figure 14. 16-bit mixed mode, word length = 24 bits dfs (mm16) din 1/ f s status (16 bits) dout status (16 bits) 128 dclks (normal mode) 256 dclks (fast mode) dac (16 bits) adc (16 bits) dac (16 bits) adc (16 bits) figure 15. 16-bit data mode, word length = 16 bits there will be a fixed relationship between the instruction cycle time of the dsp program and the ad74111, so a timer could be used to accurately control the dac updates. if a timer is not available, the multiframe-sync (mfs) mode could be used to generate a dfs pulse every 16 or 32 dclks, allowing the dsp to accurately control the number of dclks between updates using an autobuffering or dma type technique. in all cases for slave mode operation, there should be 128 dclks (normal mode) or 256 dclks (fast mode) between dac updates. the adc operates in a similar manner; however, if the dsp does not read an adc result, this will appear only as a missed sample and will not be audible. slave mode is most suited to state-machine type applications where the number of dclks and their rela tionships to the other interface signals can be controlled.
rev. 0 ad74111 ?3 1/ f s 128 dclks (normal mode) 256 dclks (fast mode) dfs (mm16) din dout dac data (24 bits) adc data (24 bits) 16 dclks dac data (24 bits) adc data (24 bits) figure 16. 16-bit data mode, word length = 24 bits 32 dclks dfs din 1/ f s dout 128 dclks (normal mode) 256 dclks (fast mode) control (16 bits) status (16 bits) dac data (16 bits) adc data (16 bits) control (16 bits) status (16 bits) figure 17. 32-bit mixed mode, word length = 16 bits 32 dclks dfs din 1/ f s dout 128 dclks (normal mode) 256 dclks (fast mode) control (16 bits) status (16 bits) control (16 bits) status (16 bits) dac data (24 bits) adc data (24 bits) figure 18. 32-bit mixed mode, word length = 24 bits 1/ f s 128 dclks (normal mode) 256 dclks (fast mode) dfs din dout dac data (24 bits) adc data (24 bits) dac data (16 bits) adc data (16 bits) figure 19. 32-bit data mode, word length = 16 bits
rev. 0 ?4 ad74111 1/ f s 128 dclks (normal mode) 256 dclks (fast mode) dfs din dout dac data (24 bits) adc data (24 bits) dac data (24 bits) adc data (24 bits) figure 20. 32-bit data mode, word length = 24 bits 1/ f s 32 dclks dac s c dac s dfs din dout adc adc c figure 21. multiframe sync 32-bit mixed mode 1/ f s 32 dclks dfs din dout dac adc dac adc figure 22. multiframe sync 32-bit data mode 1/ f s 16 dclks dfs din dout adc s dac c adc s dac c figure 23. multiframe sync 16-bit mixed mode
rev. 0 ad74111 ?5 dac dac adc adc 1/ f s 16 dclks dfs din dout figure 24. multiframe sync 16-bit data mode table iii. multiframe sync selection crd:9 crd:3 crc:2 mfs dm /mm dsp mode operating mode figure 10 0 16-bit data mode 24 10 1 32-bit data mode 22 11 0 16-bit mixed mode 23 11 1 32-bit mixed mode 21 table iv. control register map address (binary) name description type width reset setting 0 0 0 0 cra control register a r/w 10 00h 0 0 0 1 crb control register b r/w 10 00h 0 0 1 0 crc control register c r/w 10 00h 0 0 1 1 crd control register d r/w 10 08h or 09h * 0 1 0 0 cre control register e r/w 10 00h 0 1 0 1 crf control register f r 10 00h 0 1 1 0 crg control register g r/w 10 00h * 09h if din is low and 08h if din is high. table v. control word descriptions bit field description 15 r /w when this bit is high, the contents of the data field will be written to the register specified by the address field. when this bit is low, a read of the register specified by the address field will occur at the next sample interval; the contents of the data field are ignored. 14?1 register address t his 4-bit field is used to select one of the seven control registers of the ad74111. 10 reserved this bit is reserved and should always be programmed with zero. 9? data field this 10-bit field holds the data that is to be written to or read from the register specified in the address field.
rev. 0 ?6 ad74111 table vii. control register b third mclk second mclk first mclk r /w address res reserved divider divider divider 15 14, 13, 12, 11 10 9, 8, 7, 6 5, 4 3, 2 1, 0 1 0001 0 0 00 = divide by 1 00 = divide by 1 00 = divide by 1 01 = divide by 2 01 = divide by 2 01 = divide by 2 10 = divide by 4 10 = divide by 3 10 = divide by 3 11 = divide by 1 11 = divide by 1 11 = divide by 1 table viii. control register c dac and adc low group dac adc high- r /w address res reserved word width delay de-emphasis pass filter 15 14, 13, 12, 11 10 9, 8, 7, 6 5, 4 3 2, 1 0 1 0010 0 0 00 = 16 bits 0 = disabled 00 = none 0 = disabled 01 = 20 bits 1 = enabled 01 = 44.1 khz 1 = enabled 10 = 24 bits 10 = 32 khz 11 = 24 bits 11 = 48 khz table ix. control register d master/ r /w address res multiframe sync reserved dm /mm dsp mode fast dclk slave 15 14, 13, 12, 11 10 9 8, 7, 6, 5, 4 3 2 1 0 1 0011 0 0 = normal mode 0 0 = data mode 0 = 16 bits 0 = 128 f s 0 = slave 1 = mfs mode 1 = mixed mode 1 = 32 bits 1 = 256 f s 1 = master table vi. control register a adc input reference r /w address res reserved amplifier adc dac reference amplifier reserved 15 14, 13, 12, 11 10 9, 8, 7 6 5 4 3 2 1, 0 1 0000 0 0 0 = off 0 = off 0 = off 0 = off 0 = off 0 1 = on 1 = on 1 = on 1 = on 1 = on function function function function
rev. 0 ad74111 ?7 table x. control register e adcl peak adc dac r /w address res reserved enable adc gain mute mute 15 14, 13, 12, 11 10 9, 8, 7, 6 5 4, 3, 2 1 0 1 0100 0 0 0 = disabled 000 = 0 db 0 = normal 0 = normal 1 = peak enable 001 = 3 db 1 = mute 1 = mute 010 = 6 db 011 = 9 db 1xx = 12 db function table xi. control register f r /w address res reserved adc input peak level 15 14, 13, 12, 11 10 9, 8, 7, 6 5, 4, 3, 2, 1, 0 000000 = 0 dbfs 000001 = ? dbfs 0 0101 0 0 000010 = ? dbfs 111110 = ?2 dbfs 111111 = ?3 dbfs function table xii. control register g r /w address res dac volume 15 14, 13, 12, 11 10 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 0000000000 = 0 dbfs 0000000001 = (1023/1024) dbfs 1 0110 0 0000000010 = (1022/1024) dbfs 1111111110 = (2/1024) dbfs 1111111111 = mute function
rev. 0 ?8 ad74111 outline dimensions 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153ab
?9
c03069??/03(0) printed in u.s.a. ?0

▲Up To Search▲

Price & Availability of AD74111YRUZ-REEL

	To Download AD74111YRUZ-REEL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .